DocumentCode :
3242514
Title :
Implementation of Parallel LFSR-based Applications on an Adaptive DSP featuring a Pipelined Configurable Gate Array
Author :
Mucci, Claudio ; Vanzolini, Luca ; Mirimin, Ilario ; Gazzola, Daniele ; Deledda, Antonio ; Goller, Sebastian ; Knaeblein, Joachim ; Schneider, Axel ; Ciccarelli, Luca ; Campi, Fabio
Author_Institution :
ARCES, Univ. of Bologna, Bologna
fYear :
2008
fDate :
10-14 March 2008
Firstpage :
1444
Lastpage :
1449
Abstract :
Linear feedback shift registers (LFSRs) are common structures in many application fields, including cryptography, digital broadcasting and communication. High- throughput requirements need highly parallel implementations, usually accomplished in state of the art system on chips (SoCs) with application specific coprocessors. Although this approach achieves the required performance, it rapidly shows lack of flexibility when those devices are proposed, as an example, for multi-standard modems or for security applications in which run-time update can provide added value. This paper shows the implementation of parallel LFSR-based applications on an embedded adaptive DSP featuring a Pipelined Configurable Gate Array (PiCoGA). With respect to standard embedded FPGAs, pipelined devices usually provide better performance, e.g. in terms of speed, but they commonly show the undeniable drawback of additional design constraints. As a test-case, we consider the implementation of the 32-bit CRC used in the Ethernet standard that achieves on the target architecture up to ~25Gbit/sec throughput, with a parallel LFSR processing 128 bit at time, which is comparable to the performance offered by some ASIC devices.
Keywords :
digital signal processing chips; field programmable gate arrays; parallel architectures; pipeline processing; shift registers; system-on-chip; 32-bit CRC; ASIC devices; Ethernet standard; adaptive DSP; application specific coprocessors; cryptography; cyclic redundancy check; digital broadcasting- and -communication; linear feedback shift registers; multistandard modems; parallel LFSR processing; pipelined configurable gate array; standard embedded FPGA; state of the art system on chips; Adaptive arrays; Communication system security; Coprocessors; Cryptography; Digital signal processing; Digital signal processing chips; Linear feedback shift registers; Modems; System-on-a-chip; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location :
Munich
Print_ISBN :
978-3-9810801-3-1
Electronic_ISBN :
978-3-9810801-4-8
Type :
conf
DOI :
10.1109/DATE.2008.4484877
Filename :
4484877
Link To Document :
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