DocumentCode :
3242573
Title :
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography
Author :
Purnaprajna, Madhura ; Puttmann, Christoph ; Porrmann, Mario
Author_Institution :
Heinz Nixdorf Inst., Univ. of Paderborn, Paderborn
fYear :
2008
fDate :
10-14 March 2008
Firstpage :
1462
Lastpage :
1467
Abstract :
Reconfigurable architectures are being increasingly used for their flexibility and extensive parallelism to achieve accelerations for computationally intensive applications. Although these architectures provide easy adaptability, it is so with an overhead in terms of area, power and timing, as compared to non-reconfigurable ASICs. Here, we propose a low overhead reconfigurable multiprocessor, which provides both parallelism and flexibility. The architecture has been evaluated for its energy efficiency for a computational intensive algorithm used in elliptic curve cryptography (ECC). Typically, algorithms in ECC exhibit task-level parallelism and demand large amount of computational resources for custom implementations to achieve a significant speedup. A finite field multiplication in GF(2233) was chosen as a sample application to evaluate the performance on the QuadroCore reconfigurable multiprocessor architecture. A three-fold performance improvement as compared to a single processor implementation was observed. Further, via reconfiguration to suit the application, power savings of about 24% were noted in UMC´s 90 nm standard cell technology.
Keywords :
Galois fields; application specific integrated circuits; cryptography; multiprocessing systems; reconfigurable architectures; ECC; QuadroCore reconfigurable multiprocessor architecture; UMC; cell technology; computational intensive algorithm; elliptic curve cryptography; finite field multiplication; nonreconfigurable ASIC; power aware reconfigurable multiprocessor; size 90 nm; Acceleration; Computer applications; Computer architecture; Concurrent computing; Elliptic curve cryptography; Energy efficiency; Galois fields; Parallel processing; Reconfigurable architectures; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location :
Munich
Print_ISBN :
978-3-9810801-3-1
Electronic_ISBN :
978-3-9810801-4-8
Type :
conf
DOI :
10.1109/DATE.2008.4484880
Filename :
4484880
Link To Document :
بازگشت