DocumentCode :
3242632
Title :
Unified scan design with scannable memory arrays
Author :
Yano, Seiken
Author_Institution :
1st Comput. Oper. Unit, NEC Corp., Tokyo, Japan
fYear :
1995
fDate :
23-24 Nov 1995
Firstpage :
153
Lastpage :
159
Abstract :
Scan design has been popular as a design-for-testability technique. A memory array, however, has been considered non-scannable. This paper describes unified scan design that makes a memory array scannable and allows mixing of memory arrays and ordinary flip-flops in a single scan path. Based on a rule that considers ordinary flip-flops as a memory array with one word, the existing CAD system can generate the test pattern automatically without making any distinction between flip-flops and memory arrays. A long scan path involving a number of memory arrays can be split into multiple scan paths to reduce scan operation time
Keywords :
arrays; automatic testing; design for testability; fault diagnosis; flip-flops; integrated memory circuits; logic CAD; shift registers; design-for-testability; flip-flops; scan operation time; scannable memory arrays; scannable register file; single scan path; unified scan design; Automatic test pattern generation; Automatic testing; Circuit testing; Clocks; Flip-flops; Logic arrays; Logic testing; Multiplexing; Registers; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
Type :
conf
DOI :
10.1109/ATS.1995.485331
Filename :
485331
Link To Document :
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