Unified scan design with scannable memory arrays

Scan design has been popular as a design-for-testability technique. A memory array, however, has been considered non-scannable. This paper describes unified scan design that makes a memory array scannable and allows mixing of memory arrays and ordinary flip-flops in a single scan path. Based on a rule that considers ordinary flip-flops as a memory array with one word, the existing CAD system can generate the test pattern automatically without making any distinction between flip-flops and memory arrays. A long scan path involving a number of memory arrays can be split into multiple scan paths to reduce scan operation time