Title :
Static compaction for two-pattern test sets
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
We propose a static compaction procedure to reduce the size of a test set comprised of two-pattern tests. The procedure reorders the tests in the test set to maximize the number of faults detected by adjacent patterns, thus allowing some of the tests to be dropped. In addition, the procedure removes redundant tests and redundant patterns, that can be omitted without reducing the fault coverage. Experimental results are presented to evaluate the effectiveness of the compaction procedure
Keywords :
CMOS logic circuits; automatic testing; built-in self test; combinational circuits; delays; fault diagnosis; integrated circuit testing; logic testing; ATPG; CMOS stuck open faults; combinational circuits; delay faults; digital logic circuits; fault coverage; redundant patterns removal; redundant tests removal; reordering of tests; static compaction procedure; test set size reduction; two-pattern test sets; Circuit faults; Circuit testing; Cities and towns; Compaction; Delay; Electrical fault detection; Fault detection;
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
DOI :
10.1109/ATS.1995.485340
