A novel technique for noise-tolerance in dynamic circuits

Author

Goel, Sumeer ; Darwish, Tarek ; Bayoumi, Magdy

Author_Institution

Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA

fYear

2003

fDate

20-21 Feb. 2003

Firstpage

203

Lastpage

206

Abstract

Noise issues in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption issues due to aggressive scaling trends in devices and interconnections. An attempt has been made to address this problem in this paper. A new technique to make dynamic CMOS circuits noise tolerant has been proposed by the authors. Simulation results for a dynamic-CMOS NAND gate and a dynamic-CMOS 1-bit full-adder circuit show that the proposed technique has an improvement in ANTE of 6.0X over conventional dynamic logic. The proposed technique, in comparison with the twin transistor technique, proves to improve ANTE by 2.8X. There is a large power dissipation incurred during the evaluation period for certain input combinations.

Keywords

CMOS logic circuits; VLSI; adders; integrated circuit noise; logic design; logic gates; deep submicron CMOS VLSI circuits; dynamic CMOS NAND gate; dynamic CMOS adder circuit; dynamic CMOS circuits; limiter transistor technique; noise tolerant technique; noise-immunity; static power consumption; Circuit noise; Computer Society; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on

Print_ISBN

0-7695-1904-0

Type

conf

DOI

10.1109/ISVLSI.2003.1183465

Filename

1183465