DocumentCode :
3242852
Title :
On the implementation of an efficient FPGA-based CFAR processor for target detection
Author :
Cumplido, Rene ; Torres, Cesar ; Lopez, Sebastian
Author_Institution :
Computer Science Department, INAOE, P.O. Box 51 & 216, Tonantzintla, Puebla, 72000, Mexico
fYear :
2004
fDate :
8-10 Sept. 2004
Firstpage :
214
Lastpage :
218
Abstract :
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three version of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The proposed architecture has been implemented on a Field Programmable Gate Array (FPGA) device providing good performance improvements over software implementations. FPGA implementation results are presented and discussed.
Keywords :
Algorithm design and analysis; Background noise; Backscatter; Computer architecture; Digital signal processing; Field programmable gate arrays; Hardware; Object detection; Signal processing algorithms; Working environment noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Electronics Engineering, 2004. (ICEEE). 1st International Conference on
Conference_Location :
Acapulco, Mexico
Print_ISBN :
0-7803-8531-4
Type :
conf
DOI :
10.1109/ICEEE.2004.1433879
Filename :
1433879
Link To Document :
بازگشت