Title :
An area-efficient Euclidean algorithm block for Reed-Solomon decoder
Author_Institution :
Dept. of Electr. & Comput. Eng., Connecticut Univ., Storrs, CT, USA
Abstract :
This paper presents a new area-efficient architecture to implement the Euclidean algorithm, which is frequently used in Reed-Solomon decoders. The RS (255,239) decoder using the Euclidean algorithm has been implemented with 0.13 μm CMOS technology with a supply voltage of 1.1 V. We investigate hardware complexity, clock frequency and data processing rate for this Euclidean algorithm block. The results show that the total number of gates is about 44,700 and it has a data processing rate of 2.4 Gbits/s at a clock frequency of 300 MHz. As compared to the other RS decoders, it gains significant improvements in hardware complexity and latency.
Keywords :
CMOS digital integrated circuits; Reed-Solomon codes; decoding; 0.13 micron; 1.1 V; 2.4 Gbit/s; 300 MHz; CMOS technology; RS (255,239) decoder; Reed-Solomon decoder; area-efficient Euclidean algorithm block; clock frequency; data processing rate; hardware complexity; latency; supply voltage; CMOS process; CMOS technology; Clocks; Data processing; Decoding; Delay; Frequency; Hardware; Reed-Solomon codes; Voltage;
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
DOI :
10.1109/ISVLSI.2003.1183468
