Title :
Systolic array implementation of block based Hopfield neural network for pattern association
Author :
Seow, Ming-Jung ; Ngo, Hau ; Asari, Vijayan
Author_Institution :
Dept. of Electr. & Comput. Eng., Old Dominion Univ., Norfolk, VA, USA
Abstract :
This paper suggests a systolic array implementation of block based Hopfield neural network architecture using completely digital circuits. The design is based on rewriting the energy equation of the Hopfield neural network to a systolic (or modular) form. The performance of the proposed architecture is evaluated by applying various binary inputs and it is observed that the network provides massive parallelism and can be extended by cascading identical chips.
Keywords :
Hopfield neural nets; VLSI; digital integrated circuits; neural chips; neural net architecture; pattern matching; systolic arrays; APEX family; FPGA; Hopfield neural network architecture; VLSI circuit; block based Hopfield neural network; digital circuits; massive parallelism; pattern association; systolic array implementation; Artificial neural networks; Biological neural networks; Brain modeling; Computer architecture; Computer networks; Digital circuits; Hopfield neural networks; Neurons; Parallel processing; Systolic arrays;
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
DOI :
10.1109/ISVLSI.2003.1183471
