Title :
Self-timed design with dynamic domino circuits
Author :
Yang, Jung-Lin ; Brunvand, Erik
Author_Institution :
Utah Univ., Salt Lake City, UT, USA
Abstract :
We introduce a simple hierarchical design technique for building high-performance self-timed components using dynamic domino-style circuits. This technique is useful for building handshaking style functional blocks and for self-timed data path components. We wrap the dynamic domino circuit in a wrapper that communicates using a request/acknowledge protocol and mediates the pre-charge/evaluate cycle of the dynamic logic. We apply standard bundled delay matching for completion detection but add an early completion feature that can signal completion if function validity can be determined from the output value. The circuit overhead required for this early-acknowledge feature is relatively small, but can provide measurable speedup in some situations. We call this approach semi-bundled delay (SBD).
Keywords :
CMOS logic circuits; asynchronous circuits; logic design; protocols; timing; bundled delay matching; completion detection; dynamic domino-style circuits; dynamic logic; early completion feature; handshaking style functional blocks; hierarchical design technique; request/acknowledge protocol; self-timed data path components; self-timed design; semi-bundled delay; wrapper; Buildings; Delay; Digital arithmetic; Digital systems; Encoding; Latches; Logic circuits; Protocols; Signal generators; Velocity measurement;
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
DOI :
10.1109/ISVLSI.2003.1183473