A Modal of ATS Hardware and UUTS using the Graph Theory and Its Application

In the test program (TP) programming course, the testing or stimulating paths are usually searched manually. Using this approach may lead to path conflict, which would damage the unit under test (UUT) and the ATS. This paper introduces a model of ATS hardware and UUTs using the graph theory. In this model, the undigraph is used to describe the ATS hardware and UUTs. The vertexes of undigraph could describe simulating resources of instruments, simulating points of UUTs, testing resources of instruments, test points of UUTs, ports of switches and so on. The edges of undigraph could describe linking wires, switches, signal adjusting circuits, linking instruments and so on. In this model, stimulating paths and testing paths are searched automatically using the Dijkstra arithmetic; the optional instruments and paths will be selected and stored automatically; and the potential damage will be avoided. As the system model is signal-based, TP of the ATS will not mention the drivers of instruments and switches, which could reduce the maintenance cost of ATS.