DocumentCode :
3243222
Title :
Generation of tenacious tests for small gate delay faults in combinational circuits
Author :
Takahashi, Hiroshi ; Watanabe, Takashi ; Takamatsu, Yuzo
Author_Institution :
Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
fYear :
1995
fDate :
23-24 Nov 1995
Firstpage :
332
Lastpage :
338
Abstract :
In this paper, we present a test for small gate delay faults in combinational circuits, called a tenacious test and describe a method for generating tenacious tests. We consider a single gate delay fault in a circuit on the assumption of that each gate has some appropriate gate delay. First, we introduce a tenacious test ⟨V1, V2⟩ for a small gate delay fault on line L. The tenacious test ⟨V1, V2⟩ can propagate the effect of a small gate delay fault at line L to primary outputs by the delay effect. Next, we present a method for generating tenacious tests by using a timed seven-valued calculus with consideration of delay of each gate in a circuit under test. Finally, experimental results are demonstrated for gate delay faults on ISCAS´85 benchmark circuits. Experimental results show that we can obtain tenacious tests for small gate delay faults with high fault coverage
Keywords :
combinational circuits; delays; fault diagnosis; logic testing; ISCAS´85 benchmark circuits; combinational circuits; fault coverage; single gate delay fault; small gate delay faults; tenacious tests; test generation; Circuit faults; Circuit testing; Combinational circuits; Delay effects; Delay lines; Electrical fault detection; Fault detection; Hazards; Propagation delay; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
Type :
conf
DOI :
10.1109/ATS.1995.485357
Filename :
485357
Link To Document :
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