A programmable systolic device for quadratic surface generation

Systolic array architectures are favorable for special-purpose systems, as they are simple and offer a high degree of concurrency. Here, a programmable systolic device is designed to cater for the two basic tasks-subdivision and curve generation-in free-form design using quadratic B-splines. The design consists of a systolic memory matrix accessible via a rotation operation by a linear array of simple processing elements. The processing elements used are sufficiently small and simple to allow a large number of processing elements to be incorporated in the design. In particular, it is technically feasible to have as many processing elements as the number of rows on the screen