Title :
Low power design and its testability
Author :
Ueda, Hiroaki ; Kinoshita, Kozo
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
Abstract :
In this paper, we propose a power reduction tool named PORT, which evaluates the power dissipation factor Φ by utilizing the transition probability, and which reduces Φ by utilizing sets of permissible functions. Experimental results show the usefulness of PORT. Next, we will consider on the testability of circuits transformed by PORT. The size of the test set generated by compact test set generator, the number of redundant faults and the number of paths are used as testability parameters for detecting stuck-at and delay faults. Experimental results show that the test size of the circuit transformed by PORT is smaller than or equal to that of original one, but transformations by PORT increase the number of paths
Keywords :
CMOS logic circuits; automatic test software; delays; design for testability; fault diagnosis; fault location; logic CAD; logic testing; probability; CMOS circuit; PORT; delay faults; low power design; power dissipation factor; power reduction tool; redundant faults; stuck-at faults; testability; testability parameters; transition probability; CMOS logic circuits; Capacitance; Circuit faults; Circuit testing; Clocks; Delay; Electrical fault detection; Fault detection; Power dissipation; Semiconductor device modeling;
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
DOI :
10.1109/ATS.1995.485361
