DocumentCode :
3243422
Title :
Fast functional testing of delay-insensitive circuits
Author :
Pagey, Sandeep
Author_Institution :
Cadence Design Syst. Ltd., Noida, India
fYear :
1995
fDate :
23-24 Nov 1995
Firstpage :
375
Lastpage :
381
Abstract :
Although the advantages of delay-insensitive and self-timed circuits with respect to speed and operation are known, their advantages in terms of testing are not examined. We focus our attention on testing four-phase handshake signalling based circuits designed using Martin´s method. Due to the distributed nature of the control part of a delay-insensitive circuit, it is possible to simultaneously test many non-interfering portions of the circuit, thereby substantially reducing the testing time. In order to ensure that the circuit performs in a delay-insensitive manner even during testing, certain OR gates in the synthesized circuit required to be replaced by OR/C blocks. An OR/C block operates as an OR gate during normal operation and as a C-element during testing. Identification of the OR gates to be replaced by OR/C blocks and the generation of test sequences is performed by analyzing the program flow graph of the given circuit
Keywords :
asynchronous circuits; delays; design for testability; logic CAD; logic testing; Martin´s method; OR gates; OR/C blocks; delay-insensitive circuits; distributed circuit; four-phase handshake signalling; functional testing; generation of test sequences; program flow graph; self-timed circuits; testing time; Asynchronous circuits; Automatic testing; Circuit faults; Circuit synthesis; Circuit testing; Delay; Electrical fault detection; Fault detection; Flow graphs; Protocols;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
Type :
conf
DOI :
10.1109/ATS.1995.485363
Filename :
485363
Link To Document :
بازگشت