Title :
Testing of a parallel ternary multiplier using I2L logic
Author :
De, Mallika ; Sinha, Bhabani P.
Author_Institution :
USIC, Kalyani Univ., West Bengal, India
Abstract :
A generalized model for faults in multivalued I2L circuits has been proposed. Using this model, the test sets have been generated for testing the basic modules of a parallel multiplier using multivalued I2L technology. These basic modules include four input balanced ternary full adder and a precarry generator, each of which has multivalued current inputs and outputs. The generated test sets can detect single faults (either `stuck-at´ or `skew´ type) in these circuits
Keywords :
adders; design for testability; digital arithmetic; fault diagnosis; fault location; integrated injection logic; logic design; logic testing; multiplying circuits; multivalued logic circuits; I2L logic; adder; generalized model; generated test sets; input balanced ternary full adder; multivalued I2L circuits; multivalued current inputs; multivalued current outputs; parallel multiplier; parallel ternary multiplier; precarry generator; skew fault; stuck-at fault; test sets; Adders; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Mirrors; Multivalued logic; Switches;
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
DOI :
10.1109/ATS.1995.485365
