VLSI pipelined trees and pyramids for image processing

The authors consider architectures directly implementing algorithms for real-time image processing (low-level processing or image coding). Well-known real-time architectures, capable of generating and processing pyramids and of granting the required performance by using fine-grained parallelism, adopt large quantities of mesh- or pyramid-connected small processing elements (PEs), each PE executing the same basic algorithmic steps. New architectures are presented that adopt one-dimension pipelines, constituted by a linear array of stages, each stage consisting of two cascaded modules: one PE and one commutator module (to modify the ordering of pixel data flowing from stage to stage). Compared with mesh- and pyramid-connected structures, these pipelines are easier to implement, and techniques for overcoming production defects or failures can be applied in simpler and more reliable ways