Title :
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects
Author :
Yoneda, Tomokazu ; Fujiwara, Hideo
Author_Institution :
Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai Science City
Abstract :
This paper presents a wrapper and TAM cooptimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of (1) an ILP formulation for wrapper and transparent TAM co- optimization, and (2) a simulated annealing based heuristic approach to reduce the computational cost of the proposed ILP model. Experimental results show the effectiveness of the proposed methods compared to the previous transparency-based TAM approaches and the conventional dedicated test bus approaches.
Keywords :
circuit optimisation; integrated circuit interconnections; integrated circuit testing; simulated annealing; system-on-chip; ILP formulation; SoC functional interconnects; computational cost reduction; conventional dedicated test bus approach; simulated annealing based heuristic approach; test access mechanism; test scheduling; test time minimization; transparent TAM co-optimization method; wrapper configuration; Cities and towns; Computational efficiency; Computational modeling; Concurrent computing; Information science; Optimal scheduling; Sequential analysis; Simulated annealing; Testing; Time factors; SoC test; TAM; reuse of interconnect; wrapper;
Conference_Titel :
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location :
Munich
Print_ISBN :
978-3-9810801-3-1
Electronic_ISBN :
978-3-9810801-4-8
DOI :
10.1109/DATE.2008.4484929
