Title :
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits
Author :
Feinstein, David Y. ; Thornton, Mitchell A. ; Miller, D. Michael
Author_Institution :
Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX
Abstract :
This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.
Keywords :
electronic design automation; logic CAD; logic circuits; logic testing; ISCAS85 benchmarks; bijective functions; gate modification; irreversible logic circuits; partially redundant logic detection; quantum logic benchmarks; reversible logic circuits; symbolic equivalence checking; Automatic logic units; Circuit simulation; Circuit synthesis; Circuit testing; Computer science; Logic circuits; Logic design; Logic gates; Logic testing; Redundancy;
Conference_Titel :
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location :
Munich
Print_ISBN :
978-3-9810801-3-1
Electronic_ISBN :
978-3-9810801-4-8
DOI :
10.1109/DATE.2008.4484932