Challenges in chip/processor level thermal engineering

Advances in microfabrication processes and ever increasing demand for faster processing of information have led to a continuous miniaturization of microelectronic devices and interconnects. However, as the minimum feature size and design rules for state-of-art transistors and interconnects approaches sub 100 nm lengthscales, a variety of thermally induced and/or related problems such as self-heating, sub-continuum localized heating effect [1,2], failure due to electrostatic discharge (ESD), electromigration, and electrical overstress [2,3]; and RC delay [2,3] emerge that need to be addressed urgently. In addition, the continuous trend to pack more transistors on a single chip result in an unprecedented level of power dissipation, and therefore higher temperatures at the chip and packaging level. Also, more recently, there has been a big interest in system on a chip (SOC). On a single chip, it is possible to combine many components such as memory and logic. The application is broad ranging from portable or hand held devices to high end workstations. The importance of SOC has been emphasized on the International Technology Roadmap for Semiconductors (ITRS).