DocumentCode
3243876
Title
A DSP based bit-synchronization algorithm
Author
Loos, Timothy S.
Author_Institution
Raytheon E-Systems, Richardson, TX, USA
Volume
3
fYear
1997
fDate
2-5 Nov 1997
Firstpage
1397
Abstract
This paper describes a software based bit-sync algorithm implemented on a fixed point digital signal processor (DSP). This implementation is used to process the audio output from a radio. It is a minimal hardware implementation. It employs a bit-sync algorithm which is a modification of the lead-lag digital phase-lock loop (LL-DPLL) algorithm of Cessna and Levy (1972)
Keywords
audio signals; digital phase locked loops; digital signal processing chips; radio receivers; DSP based bit-synchronization algorithm; LL-DPLL algorithm; audio output; bit-sync algorithm; fixed point digital signal processor; lead-lag digital phase-lock loop; minimal hardware implementation; radio output; software based bit-sync algorithm; Baseband; Circuits; Clocks; Cutoff frequency; Digital signal processing; Filters; Hardware; Signal processing; Signal processing algorithms; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
MILCOM 97 Proceedings
Conference_Location
Monterey, CA
Print_ISBN
0-7803-4249-6
Type
conf
DOI
10.1109/MILCOM.1997.644997
Filename
644997
Link To Document