• DocumentCode
    3244169
  • Title

    Program Optimization of Array-Intensive SPEC2k Benchmarks on Multithreaded GPU Using CUDA and Brook+

  • Author

    Wang, Guibin ; Tang, Tao ; Fang, Xudong ; Ren, Xiaoguang

  • Author_Institution
    Nat. Lab. for Parallel & Distrib. Process., Nat. Univ. of Defense Technol., Changsha, China
  • fYear
    2009
  • fDate
    8-11 Dec. 2009
  • Firstpage
    292
  • Lastpage
    299
  • Abstract
    Graphic Processing Unit (GPU), with many light-weight data-parallel cores, can provide substantial parallel computing power to accelerate several general purpose applications. Both the AMD and NVIDIA corps provide their specific high performance GPUs and software platforms. As the floating-point computing capacity increases continually, the problem of ``memory-wall´´ becomes more serious, especially for array-intensive applications. In this paper, we optimize and implement two SPEC2k benchmarks mgrid and swim on multithreaded GPU using CUDA and Brook+. In order to reduce the pressure on off-chip memory, we make use of data locality in multi-level memory hierarchies and hide long memory access latency via double-buffers. To balance inter-thread parallelism and intra-thread locality, we further tune thread granularity for each kernel and empirically study the best equilibrium point for this problem. Flow control instruction can significantly impact the effective instruction throughput. Oriented to this problem, we introduce a diverge elimination technology to convert condition expression into computing operation. Through all the optimizations, we gain the speedup of 10×-34× to the CPU implementation on the GPUs of AMD and NVIDIA respectively. Finally, we summarize and compares the GPUs from AMD and NVIDIA in hardware and software.
  • Keywords
    computer graphics; coprocessors; multi-threading; Brook+; CUDA; array intensive SPEC2k benchmark; data locality; floating point computing; flow control instruction; graphic processing unit; interthread parallelism; intrathread locality; lightweight data parallel core; memory access latency; memory wall problem; multilevel memory hierarchy; multithreaded GPU; off-chip memory pressure reduction; parallel computing; program optimization; Acceleration; Application software; Central Processing Unit; Delay; Graphics; Kernel; Parallel processing; Software performance; Throughput; Yarn; Brook+; CUDA; GPGPU; mgrid; optimization; swim;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Systems (ICPADS), 2009 15th International Conference on
  • Conference_Location
    Shenzhen
  • ISSN
    1521-9097
  • Print_ISBN
    978-1-4244-5788-5
  • Type

    conf

  • DOI
    10.1109/ICPADS.2009.12
  • Filename
    5395276