Low power implementation of fast addition algorithms

Author

Allam, M.W. ; Elmasry, M.I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

2

fYear

1998

fDate

24-28 May 1998

Firstpage

645

Abstract

As portable multimedia and communications applications emerge, the need for low power digital circuits becomes more prominent. The addition process is the most used operation in any DSP because addition is involved in all other mathematical operations. Therefore, adder design is considered critical because it influences the performance of the system in terms of power and delay. In this paper, we review some of the fast addition algorithms. We also introduce power, delay and area comparison based on a 16 bit adder implemented in each algorithm

Keywords

CMOS logic circuits; VLSI; adders; carry logic; integrated circuit design; logic design; reviews; 16 bit; 16 bit adder; DSP; adder design; area; communications applications; delay; fast addition algorithms; low power digital circuits; low power implementation; performance; portable multimedia applications; Adders; Algorithm design and analysis; Arithmetic; Delay; Digital circuits; Digital signal processing; Logic circuits; Multimedia communication; Power dissipation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1998. IEEE Canadian Conference on

Conference_Location

Waterloo, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-4314-X

Type

conf

DOI

10.1109/CCECE.1998.685579

Filename

685579