• DocumentCode
    3244421
  • Title

    A statistically rigorous approach for improving simulation methodology

  • Author

    Yi, Joshua J. ; Lilja, David J. ; Hawkins, Douglas M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
  • fYear
    2003
  • fDate
    8-12 Feb. 2003
  • Firstpage
    281
  • Lastpage
    291
  • Abstract
    Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing new processor architectures, as well as when evaluating the performance of new processor enhancements. However, despite this dependence on simulators, statistically rigorous simulation methodologies are not typically used in computer architecture research. A formal methodology can provide a sound basis for drawing conclusions gathered from simulation results by adding statistical rigor, and consequently, can increase confidence in the simulation results. This paper demonstrates the application of a rigorous statistical technique to the setup and analysis phases of the simulation process. Specifically, we apply a Plackett and Burman design to: (1) identify key processor parameters; (2) classify benchmarks based on how they affect the processor; and (3) analyze the effect of processor performance enhancements. Our technique expands on previous work by applying a statistical method to improve the simulation methodology instead of applying a statistical model to estimate the performance of the processor.
  • Keywords
    computer architecture; microprocessor chips; performance evaluation; statistical analysis; virtual machines; Plackett Burman design; benchmark classification; computer architecture; key processor parameters; processor performance enhancements; simulation methodology; statistically rigorous approach; Analytical models; Application software; Computational modeling; Computer architecture; Computer simulation; Costs; Performance analysis; Space exploration; Statistical analysis; Time factors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
  • ISSN
    1530-0897
  • Print_ISBN
    0-7695-1871-0
  • Type

    conf

  • DOI
    10.1109/HPCA.2003.1183546
  • Filename
    1183546