DocumentCode :
3244484
Title :
TCP: tag correlating prefetchers
Author :
Hu, Zhigang ; Martonosi, Margaret ; Kaxiras, Stefanos
fYear :
2003
fDate :
8-12 Feb. 2003
Firstpage :
317
Lastpage :
326
Abstract :
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recently, sophisticated hardware correlating prefetching mechanisms have been proposed, in some cases coupled with some form of dead-block prediction. In many proposals, however correlating prefetchers demand a significant investment in hardware. In this paper we show that correlating prefetchers that work with tags instead of cache-line addresses are significantly more resource-efficient, providing equal or better performance than previous proposals. We support this claim by showing that per-set tag sequences exhibit highly repetitive patterns both within a set and across different sets. Because a single tag sequence can capture multiple address sequences spread over different cache sets, significant space savings can be achieved. We propose a tag-based prefetcher called a tag correlating prefetcher (TCP). Even with very small history tables, TCP outperforms address-based correlating prefetchers many times larger. In addition, we show that such a prefetcher can yield most of its performance benefits if placed at the L2 level of an aggressive out-of-order processor. Only if one wants prefetching all the way up to L1, is dead-block prediction required. Finally, we draw parallels between the two-level structure of TCP and similar structures for branch prediction mechanisms; these parallels raise interesting opportunities for improving correlating memory prefetchers by harnessing lessons already learned for correlating branch predictors.
Keywords :
cache storage; memory architecture; microprocessor chips; performance evaluation; CPU; L1 cache; L2 cache; aggressive out-of-order processor; branch prediction mechanisms; dead-block prediction; main memory; multiple address sequences; per-set tag sequences; performance; prefetching; repetitive patterns; space savings; speed gap; tag correlating prefetchers; Delay; Hardware; History; Investments; Out of order; Prefetching; Proposals; Software systems; Spine; Technical Activities Guide -TAG;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
ISSN :
1530-0897
Print_ISBN :
0-7695-1871-0
Type :
conf
DOI :
10.1109/HPCA.2003.1183549
Filename :
1183549
Link To Document :
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