DocumentCode
3244806
Title
Architectures and compilers
Author
Di Martino, Beniamino
Author_Institution
Second University of Naples
fYear
2003
fDate
5-7 Feb. 2003
Firstpage
40
Lastpage
40
Keywords
Costs; Field programmable gate arrays; Memory architecture; Parallel processing; Performance analysis; Surface-mount technology; Very large scale integration; Video compression; Wavelet domain; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel, Distributed and Network-Based Processing, 2003. Proceedings. Eleventh Euromicro Conference on
Conference_Location
Genova, Italy
ISSN
1066-6192
Print_ISBN
0-7695-1875-3
Type
conf
DOI
10.1109/EMPDP.2003.1183563
Filename
1183563
Link To Document