An adaptive multi-module cache with hardware prefetching mechanism for multimedia applications

This research is to design a high performance cache structure with a hardware prefetching mechanism that is applicable to embedded multimedia processors. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. The overhead of prefetching operation is shown to be a negligible factor. Also the accuracy of the prefetch operation is over 97% of the total number of prefetches generated. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with four or twice as much space respectively. And also, compared with a victim cache with 32-byte block size, the average miss ratio can be reduced by over twice for multimedia applications. We have also shown that power consumption in the AMMC is around 10% /spl sim/ 60% lower than these various cache systems.