Automatic generation of area constraints for FPGA implementation

FPGA devices are dominant implementation and prototyping media for digital circuits. However, FPGA implementations usually require many specific constraints such as timing constraints, area constraints to guarantee soundness and completeness of designed circuits. In conventional FPGA design flow, these constraints are built by hand using constraints editor tool. In this paper, we proposed a new approach to automatically generate area constraints. A new design flow is introduced to efficiently rapid prototype circuits with specific constraints on FPGA. This work also introduces a new tool, so-called Constraints Generator tool, to automatically generate area constraints. The created constraints are based on a list of specific elements which we want to have an especial implementation on FPGA. This list uses EDIF format to describe particular elements. Some experiments have been conducted to validate the correctness of proposed design flow and tool. The proposed approach in this paper has been applied in a research project funded by Vietnam National University Ho Chi Minh City and The Second Higher Education Project - World Bank Project.