Fuzzy/scalar RISC processor: architectural level design and modeling

Author

Patyra, Marek J. ; Braun, Eric

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Duluth, MN, USA

Volume

3

fYear

1996

fDate

8-11 Sep 1996

Firstpage

1937

Abstract

This paper presents the design and modeling issues of the fuzzy/scalar processor which is intended to perform standard scalar operations, as well as specialized fuzzy logic operations at very high speed. The reduced instruction set (RISC) architecture was chosen for the processor implementation. This high performance and, at the same time, extremely flexible device, can be used in a variety of applications where high speed standard and/or fuzzy logic operations are required. The high-level simulation results of the fuzzy/scalar reduced instruction set processor model (codename F/S RISC), are presented. The model built with Mentor Graphics “M” language was simulated using Lsim simulator at the clock frequency of 100 MHz. The current technology for the implementation of F/S RISC processor is chosen to be 1.2 μm n-well CMOS

Keywords

CMOS logic circuits; VLSI; computer architecture; fuzzy control; reduced instruction set computing; 1.2 μm n-well CMOS; architectural level design; architectural level modeling; fuzzy/scalar RISC processor; reduced instruction set architecture; specialized fuzzy logic operations; standard scalar operations; CMOS process; CMOS technology; Clocks; Frequency; Fuzzy logic; Fuzzy sets; Graphics; Process design; Reduced instruction set computing; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Fuzzy Systems, 1996., Proceedings of the Fifth IEEE International Conference on

Conference_Location

New Orleans, LA

Print_ISBN

0-7803-3645-3

Type

conf

DOI

10.1109/FUZZY.1996.552695

Filename

552695