Title :
A reconfigurable multi-chip analog neural network: recognition and back-propagation training
Author :
Tam, S. ; Holler, M. ; Brauch, J. ; Pine, A. ; Peterson, A. ; Anderson, S. ; Deiss, S.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
A multi-chip analog neural network system capable of prototyping networks with as many as 81920 synaptic connections and 1024 neurons is described. The neural network architecture is reconfigurable by routing all neuron activation values through a host computer which can re-map the network connectivity by changing a look-up table in memory. Once a network is successfully prototyped, it is hardwired and embedded in an application to take full advantage of the performance that the electrically trainable analog neural network (ETANN) chips provide. A multi-layer, multi-chip neural network containing 12660 synaptic connections designed for a pattern recognition application is described along with results. Constraints on network topologies associated with the busing architecture chosen and simulation of this multi-chip system are discussed
Keywords :
backpropagation; neural nets; pattern recognition; ETANN; back-propagation training; electrically trainable analog neural network; neural network architecture; pattern recognition; reconfigurable multi-chip analog neural network; Application software; Computer architecture; Computer networks; Multi-layer neural network; Neural networks; Neurons; Pattern recognition; Prototypes; Routing; Table lookup;
Conference_Titel :
Neural Networks, 1992. IJCNN., International Joint Conference on
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-0559-0
DOI :
10.1109/IJCNN.1992.226918