A Memory Unit for Priority Management in IPSec Accelerators

This paper introduces a hardware architecture for high speed network processors, focusing on support for quality of service in IPSec-dedicated systems. The effort is aimed at defining a secure system on chip environment, where the speed and security requirements are of utmost importance. In particular, a method is devised to introduce and support quality of service through priorities at this level. An architecture of a memory system that provides automatic priority management is proposed.