Title :
Hardware design of a color quantization with self-organizing map
Author :
Oba, Yoshiro ; Yamamoto, Kota ; Nagai, Takahiro ; Hikawa, Hiroomi
Author_Institution :
Grad. Sch. of Sci. & Eng., Kansai Univ., Suita, Japan
Abstract :
This paper discusses the use of self-organizing map (SOM) for a color quantization that reduces the number of colors used in a color image, and a SOM-based hardware color quantization system is proposed. The RGB components in the image are fed to the SOM as the input vector. Then they are quantized into a smaller number of vectors that are used to form a color palette. The SOM based color quantization system is designed by using VHDL and its feasibility is verified by the VHDL simulations. The hardware SOM used for the system includes a neighborhood function by using simple circuit. Since the search for the winning neuron and the weight updates are performed in parallel, it can process each vector element (RGB data) within a single clock cycle. Then it is confirmed that the design is synthesizable. Simulation results show that the system is capable of high quality color quantization with the speed of 34.5 ms per image and the PSNR of the reconstructed image is 30 dB in case the training iterations is 2.
Keywords :
hardware description languages; image colour analysis; self-organising feature maps; RGB components; SOM-based hardware color quantization system; VHDL simulations; color image; hardware design; neighborhood function; self-organizing map; single clock cycle; vector element; weight updates; winning neuron; Clocks; Field programmable gate arrays; Registers; Vectors; FPGA; Self organizing map; color quantization; vector quantization;
Conference_Titel :
Intelligent Signal Processing and Communications Systems (ISPACS), 2011 International Symposium on
Conference_Location :
Chiang Mai
Print_ISBN :
978-1-4577-2165-6
DOI :
10.1109/ISPACS.2011.6146079