Automatic generation of hardware self-organizing map for FPGA implementation

Self-organizing map (SOM) proposed by T. Kohonen is a neural network with unsupervised leaning to classify multidimensional vectors. The performance of the SOM implemented in software decreases as the number of neurons or vector dimention increases. Thus, performance acceleration of the SOM by the custom hardware is highly desired. However, compared to the SOM implemented in software, the modification of the hardware SOM design is still time-consuming task. This paper proposes a flexible hardware SOM configuration, and a computer program that generates VHSIC hardware description language (VHDL) code of the hardware SOM was developed.