A parallel evolutionary algorithm for circuit partitioning

As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimization and simulation, HDL-based synthesis, etc. is currently a field of increasing research activity. In some of these applications the circuit partitioning problem occurs. That implies dividing a circuit into non-overlapping subcircuits while minimizing the number of cuts after the division and balancing the load associated to each one. Very effective heuristic algorithms have been developed in order to solve this problem, but it is unknown how good the partitions are since the problem is NP-complete. In these cases the use of parallel processing can be very useful. This paper describes a parallel evolutionary algorithm for circuit partitioning, where parallelism improves the solutions found by the corresponding sequential algorithm, which indeed is quite effective compared with other previously proposed procedures.