Low-power adiabatic SRAM

This paper presents a new adiabatic static random access memory (SRAM). The proposed adiabatic SRAM uses two trapezoidal-wave pulses and resembles behavior of static CMOS 4T-SRAM. The elementary cell structure of proposed SRAM consists of two high load resistors which is constructed of PMOS, a cross-coupled NMOS pair and NMOS switch which is necessary to restrict short circuit current. From the simulation results, we show that the energy consumption of the proposed circuit is lower than that of conventional SRAM.