Title :
Architecture of the NS32532-a single chip VLSI high performance CPU
Author :
Schanin, David J.
Author_Institution :
Nat. Semicond., Santa Clara, CA, USA
fDate :
Feb. 29 1988-March 3 1988
Abstract :
The 32-bit NS32532 is fabricated in 1.25- mu m, double metal CMOS. It achieves a scalar performance of 15 MIPS (million instructions per second) peak, 8-10 MIPS average, and can execute 15 million floating point operations per second. The CPU´s four-stage instruction execution pipeline, its unique floating point arithmetic support, the architecture of its internal instruction and data caches, and its branch prediction mechanism are presented. The special instructions and cache coherency mechanisms for multiprocessing support are described.<>
Keywords :
CMOS integrated circuits; VLSI; digital arithmetic; microprocessor chips; 1.25 micron; 15 FLOPS; 15 MIPS; 32 bit; 8 to 10 MIPS; NS32532; branch prediction mechanism; data caches; double metal CMOS; floating point arithmetic support; four-stage instruction execution pipeline; internal instruction; multiprocessing support; scalar performance; single chip VLSI high performance CPU; Bandwidth; Central Processing Unit; Circuits; Computer architecture; Decoding; Floating-point arithmetic; Hardware; Pipelines; Registers; Very large scale integration;
Conference_Titel :
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-0828-5
DOI :
10.1109/CMPCON.1988.4860
