On-line error detection and correction techniques for TSV in three-dimensional integrated circuit

This paper presents an on-line error detection and correction techniques for through silicon via (TSV) in three-dimensional integrated circuit (3-D IC). The proposed architecture is based on biresidue codes to detect and correct the error on-line in the failed TSV over syndrome analysis. Experimental results show the proposed design has good performance in area and TSV overhead and improves the yield of TSV up to 99.9%.