Defect reduction for 20nm high-k metal gate technology

This paper describes the methodology, results and improvements for defect reduction in the Front End of Line of a 20 nm planar technology. The defect inspection optimization and defect reduction methodology described were implemented for the High-k Metal Gate (HKMG) stack module on 300 mm wafers for high performance logic devices. Along with new technological advances, reduction of critical defects becomes increasingly important. The introduction of a multi-level HKMG stack material is a key challenge in terms of yield limiting defects. The multiple materials interfaces lead to an increased variety of defect mechanisms in the gate module. As a consequence, defect management in the gate stack has become critical to a successful yield ramp. From a defect management perspective, the HKMG stack has some unique characteristics. Very small defects in the gate module at earlier steps can lead to larger and more yield-impacting defects at later steps, as layers are deposited on each other. These critical defects are often difficult to detect after the gate patterning step but can be more easily detected at the deposition steps. The detection at the deposition steps will increase the detection probability (capture-rate of those critical defects) and will result in finding the defects closer to the defect source. Particularly if the defect was caused by the deposition / clean steps and not the patterning process steps.