Automatic design for bit-serial MSPA architecture

Author

Kunieda, Hiroaki ; Liao, Yusong ; Li, Dongju ; Ito, Kazuhito

Author_Institution

Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

27

Lastpage

32

Abstract

A memory sharing processor array (MSPA) architecture is effective in both data storage and processor cell utilization efficiency. In this paper, the design methodology for MSPA is extended to synthesise a bit-serial datapath. As a synthesis example, we propose a new bit-serial multiplier with a smaller number of logic gates than conventional bit-serial multipliers

Keywords

digital signal processing chips; logic CAD; logic gates; multiplying circuits; systolic arrays; bit-serial MSPA architecture; bit-serial datapath synthesis; bit-serial multiplier; computer architecture; data storage; design automation; design methodology; logic gates; memory sharing processor array; processor cell utilization; Design methodology; Electronic mail; Hardware; Indium tin oxide; Logic gates; Memory; Processor scheduling; Resource management; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486197

Filename

486197