Optimization of Cost Function with Cell Library Placement of VLSI Circuits Using Simulated Annealing

VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive solution of the cell placement technique, with emphasis on standard cell and macro cell placement using simulated annealing. The metropolis algorithm is applied to generate generations by decreasing the temperature (cooling coefficient). The state will be accepted or rejected based on energy level (cost) and finally optimum solution will be selected.