DocumentCode
3246672
Title
The NS32605 cache controller
Author
Quinones, Lisa K.
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA, USA
fYear
1988
fDate
Feb. 29 1988-March 3 1988
Firstpage
218
Lastpage
222
Abstract
A description is given of the NS32605 cache controller, currently under development, which integrates the tag store, control logic, and data buffering into a single VLSI component. The controller supports up to 256/kbytes of external cache memory, as well as a variety of caching protocols and configurations. The discussion covers the maximization of cache performance, processor port optimization, system port optimizations, parity support, and scalability and partitioning.<>
Keywords
VLSI; buffer storage; integrated memory circuits; microprocessor chips; storage management; 256 kB; NS32605 cache controller; VLSI component; cache performance; caching protocols; control logic; data buffering; external cache memory; parity support; partitioning; processor port optimization; scalability; tag store; Cache memory; Clocks; Computer buffers; Control systems; Costs; Delay; Logic; Multiprocessing systems; Protocols; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-0828-5
Type
conf
DOI
10.1109/CMPCON.1988.4862
Filename
4862
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