Title :
A scheduling algorithm for synthesis of bus-partitioned architectures
Author :
Moshnyaga, Vasily G. ; Ohbayashi, Fumiaki ; Tamaru, Keikichi
Author_Institution :
Dept. of Electron. & Commun., Kyoto Univ., Japan
fDate :
29 Aug-1 Sep 1995
Abstract :
Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach for integrated scheduling and interconnect binding of bus-segmented data-paths. Experiments show that the approach provides better results than existing methods and is quite flexible
Keywords :
computer architecture; integrated circuit interconnections; logic CAD; scheduling; bus-partitioned architectures; bus-segmented data-paths; interconnect binding; scheduling; scheduling algorithm; sub-micron chip design; CMOS technology; Chip scale packaging; Clocks; Delay; Differential equations; Registers; Scheduling algorithm; Switches; Timing; Topology;
Conference_Titel :
Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
Conference_Location :
Chiba
Print_ISBN :
4-930813-67-0
DOI :
10.1109/ASPDAC.1995.486200
