Synthesis of false loop free circuits

In behavior synthesis, an improper resource sharing may result in a circuit containing false loops which is non-simulatable or non-timing-analyzable. Previous approaches solve this problem during the datapath allocation phase. To build a false loop free circuit, they may have to allocate additional functional units other than those defined in the resource constraints. In this paper, we present an approach to solve the problem during the scheduling phase. Our scheduling algorithm finds a schedule which guarantees to have a false loop free circuit mapping under the given resource constraints. Experiments show the proposed approach finds false loop free schedule for most of the examples without introducing extra control steps