Application of partially bonded SOI structure to an intelligent power device having vertical DMOSFET

In recent years, many types of Intelligent Power Devices (IPDs) have been developed. A key technology of developing the IPDs is the isolation between power device and control circuit. The isolation structures and its manufacturing methods are required to be more efficient and cost effective. We had been developed a low side switch IPD having Vertical DMOSFET (VDMOS) output by using poly-crystalline silicon sandwiched wafer bonding (PSB) technique. In this PSB structure, it is easy to achieve void-free bonding because the extremely flat poly-crystalline silicon (poly-Si) layer surface and the single-crystalline silicon (Si) substrate surface are bonded together. However, the PSB structure is still expensive. To reduce the fabrication cost, we have made a study of the direct bonding without poly-Si and proposed a new SOI structure named partially bonded (PB) structure. This paper reports the evaluation results that we applied the PB structure to a low side switch IPD for the first time