Architectural simulation for a programmable DSP chip set

Author

Lee, Jong Tae ; Kim, Jaemin ; Son, Jae Cheol

Author_Institution

Semicond. Div., Samsung Electron. Co. Ltd., Kyungki, South Korea

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

171

Lastpage

176

Abstract

This paper presents an architectural simulator called VIDEOFLOW software tools for developing programmable DSP chip set for various video codec standards. This DSP chip set consists of the Image Compression Coprocessor (ICC) and Motion Estimation Coprocessor (ICC), which provide an easy solution for implementing the major digital video codec algorithms. The ICC/MEC simulation components are 100 percent bit accurate and closely approximate the timing of the actual chips. In addition, the simulation tool provides users with the ICC/MEC system simulation, debugging, and various performance monitors. This tool can also be used to define and modify the architectural specification for future product line of the ICC and MEC

Keywords

circuit analysis computing; data compression; digital signal processing chips; image coding; logic CAD; motion estimation; programmable logic devices; DSP chip set; Image Compression Coprocessor; Motion Estimation Coprocessor; VIDEOFLOW; architectural simulator; debugging; performance monitors; programmable DSP chip set; simulation tool; video codec standards; Code standards; Coprocessors; Digital signal processing chips; Image coding; Motion estimation; Software standards; Software tools; Standards development; Timing; Video codecs;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486219

Filename

486219