Logic optimization by an improved sequential redundancy addition and removal technique

Logic optimization methods using automatic test pattern generation (ATPG) techniques such as redundancy addition and removal have recently been proposed. We generalize this approach for synchronous sequential circuits. We proposed several new sequential transformations which can be efficiently identified and used for optimizing large designs. One of the new transformations involves adding redundancies across time frames in a sequential circuit. We also suggest a new transformation which involves adding redundancies to block initialization of other wires. We use efficient sequential ATPG techniques to identify more sequential redundancies for either addition or removal. We have implemented a sequential logic optimization system based upon this approach. We show experimental results to demonstrate that this approach is both CPU time efficient and memory efficient and can optimize large sequential designs significantly