DocumentCode
3247714
Title
Digital vision chips and high-speed vision systems
Author
Ishikawa, M. ; Komuro, T.
Author_Institution
Dept. of Inf. Phys. & Comput., Tokyo Univ., Japan
fYear
2001
fDate
14-16 June 2001
Firstpage
1
Lastpage
4
Abstract
Conventional image processing has a critical limit of frame rate derived from serial transmission of the video signal. In order to overcome the limit, fully parallel processing architecture without scanning has been proposed. In this paper, vision chips with digital circuits and high speed application systems developed in our laboratory are described.
Keywords
VLSI; computer vision; digital signal processing chips; parallel architectures; digital vision chips; frame rate; fully parallel processing architecture; high speed application systems; high-speed vision systems; Analog circuits; Detectors; Digital circuits; Image processing; Laboratories; Machine vision; Physics; Random access memory; Retina; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934175
Filename
934175
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