Fanout-tree restructuring algorithm for post-placement timing optimization

Author

Aoki, T. ; Murakata, M. ; Mitsuhashi, T. ; Goto, N.

Author_Institution

Semicond. DA & Test Eng. Center, Toshiba Co. Ltd., Kawasaki, Japan

fYear

1995

fDate

29 Aug-1 Sep 1995

Firstpage

417

Lastpage

422

Abstract

This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average

Keywords

circuit layout; circuit layout CAD; timing; fanout-tree restructuring; interconnection RC delay; post-placement timing optimization; routability; timing constraints; timing optimization; Capacitance measurement; Constraint optimization; Degradation; Delay estimation; Design optimization; Integrated circuit interconnections; Logic design; Semiconductor device testing; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal

Conference_Location

Chiba

Print_ISBN

4-930813-67-0

Type

conf

DOI

10.1109/ASPDAC.1995.486266

Filename

486266