DocumentCode
3247845
Title
480 ps 64-bit race logic adder
Author
Se-Joong Lee ; Ramchan Woo ; Hoi-Jun Yoo
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
fYear
2001
fDate
14-16 June 2001
Firstpage
27
Lastpage
28
Abstract
In this paper, a high-speed 64-bit carry look-ahead adder is implemented by race logic for fast carry generation. G/sup 1/g/G/sup 1/k (Level 1 Group Generate/Kill) and G/sup 2/g/G/sup 2/k (Level 2 Group Generate/Kill) stages are designed by race logic. The adder consists of 4-stages, and clk-S63 delay is 480 ps with 0.18 /spl mu/m CMOS technology.
Keywords
CMOS logic circuits; adders; carry logic; high-speed integrated circuits; 0.18 micron; 480 ps; 64 bit; CMOS technology; G/sup 1/g/G/sup 1/k stage; G/sup 2/g/G/sup 2/k stage; carry generation; high-speed carry look-ahead adder; race logic adder; Adders; Boolean functions; CMOS logic circuits; CMOS technology; Clocks; Delay; Logic circuits; Logic design; Switches; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934183
Filename
934183
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