Title :
A cell transistor scalable array architecture for high-density DRAMs
Author :
Takashima, D. ; Nakano, H.
Author_Institution :
Toshiba Corp., Yokohama, Japan
Abstract :
The limitation of DRAM cell transistor scalability is a severe problem in scaled DRAMs. A DRAM requires thicker gate oxide than that in logic LSIs, because a high wordline voltage must be applied to a memory cell transistor in order to write "1" data into the cell capacitor via the cell transistor. A new DRAM array architecture for scaled DRAMs is proposed. This scheme reduces stress bias for cell transistors, and enables the cell transistor to shrink without speed penalty.
Keywords :
DRAM chips; cellular arrays; memory architecture; array architecture; cell capacitor; cell transistor scalability; gate oxide; high-density DRAMs; scalable array architecture; stress bias; wordline voltage; Capacitors; Leakage current; Logic arrays; Logic devices; Random access memory; Scalability; Stress; Threshold voltage; Tin; Writing;
Conference_Titel :
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-014-3
DOI :
10.1109/VLSIC.2001.934185
