DocumentCode
3247899
Title
Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM
Author
Kyunam Lim ; Sangseok Kang ; Jonghyun Choi ; Jaehoon Joo ; Younsang Lee ; Jinseok Lee ; Sooin Cho ; Byungil Ryu
fYear
2001
fDate
14-16 June 2001
Firstpage
33
Lastpage
34
Abstract
Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of 100 ms for the data retention time (tREF) using the BLC scheme. BLC scheme also improves the low VCC margin by 0.3 V and the RAS to CAS delay time (tRCD) by 1.5 ns. Differential current evaluation for the E-fuse implementation shows polysilicon fuse fail rate <10/sup -12/.
Keywords
DRAM chips; electric fuses; integrated circuit reliability; integrated circuit yield; bit line coupling scheme; data retention time; delay time; electrical fuse circuit; field programmable repair scheme; high density DRAM; polysilicon fuse fail rate; yield; Boosting; Capacitance; Capacitors; Content addressable storage; Coupling circuits; Fuses; Latches; Product design; Random access memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934186
Filename
934186
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